The present invention relates generally to metal-oxide-semiconductor (MOS) devices, and more particularly to methods for manufacturing high performance MOS field effect devices adapted for large scale integration on semiconductor substrates. The invention further relates to non-planar MOS devices characterized by submicron channel widths.
Metal-oxide-semiconductor field effect devices conventionally include source and drain regions formed on the upper surface of a silicon wafer, interconnected by a channel region. A gate electrode is disposed overlying the channel region, insulated from it by a thin film of oxide or other suitable dielectric. Current flow between the source and drain regions is controlled by applying a voltage to the gate electrode.
The performance (i.e., the frequency response or switching speed) of such a device depends on the dimensions of its components, particularly the length of its channel. Normally, the channel length of an MOS device is determined by the photolithographic and impurity diffusion processes used to form its source and drain regions. As conventionally practiced, these processes do not permit the formation of as short a channel as desired for maximum performance.
Several high performance MOS technologies have been developed in recent years. These include a scaled-down silicon gate MOS process called H-MOS by its principal proponent; V-MOS (for "vertical MOS"), a double-diffusion process featuring anisotropic etching of a V-shaped groove in the silicon wafer; and a planar double-diffusion process called D-MOS. While these technologies all are capable of producing devices having switching speeds approaching those of bipolar devices, none is without its disadvantages. For example, H-MOS, which relies on scaling down the size and parameters of conventional planar MOS devices, places great demands on a manufacturer's ability to form very fine patterns accurately and reproducibly. The production of V-MOS devices requires the use of two relatively high cost processes: epitaxial deposition and anisotropic etching. D-MOS, in which channels are defined by successive diffusions of n- and p-type impurities through the same mask opening, requires a precise diffusion source and superior process control to achieve narrow channel widths reproducibly. In addition, both H-MOS and D-MOS share the disadvantage (in applications requiring high packing density) of being planar processes, which require more wafer surface area than non-planar processes such as V-MOS.